Performance of computers, data handling systems, information systems and, particularly, graphic display systems is highly dependent on memory performance. Continuing improvements in memory bandwidth and latency performance directly relate to increased usefulness and productivity of these various systems.
Improvements in memory technology basically refer to improvements in memory density and memory speed. Various techniques have been implemented to improve memory speed performance. One such technique utilizes interleaved memory. Memory chips are typically organized in banks so that, instead of a single word, multiple data words are read or written at one time. The memory banks are one word wide so that the width of a memory bank does not change, but addresses are sent to several banks simultaneously, so that all memories are accessed at one time. While consecutive memory write operations normally require that a later write operation must wait for an earlier operation to finish, separation of memory into banks allow one clock cycle for each write operation, so long as the write operations are not directed to the same memory bank. Accordingly, the mapping of addresses to memory banks affects the speed performance of the memory. An interleaved memory improves memory speed performance by optimizing sequential memory accesses and allowing multiple independent memory accesses. Utilization of multiple memory controllers allows memory banks to operate independently. However, interleaved memory techniques unfortunately have some disadvantages. One disadvantage is that interleaved memories generally require multiple memory chips, increasing the size and expense of a memory system. Another disadvantage of interleaved memories is the difficulty of main memory expansion. Because memory control hardware is likely to control equal-sized memory banks, memory expansion will generally require doubling of a memory size.
Another technique for improving memory speed performance is usage of fast page mode operation. Dynamic random access memories (DRAMs), in general, are accessed by dividing memory accesses into row accesses and column accesses. Each row access results in a row of bits buffered inside the DRAM for subsequent column accesses. Typically, a DRAM row size is the square root of the DRAM size. Fast page mode operation optimizes memory speed performance by supplying timing signals that allow repeated accesses to the row buffer without repeating the time required for a row access. Thus, the individual bits inside the row buffer are accessed much as a static RAM is accessed--the bits are accessed randomly in the buffer by changing the column address until the next row access takes place. An advantage of fast page mode operation is that the optimization is achieved using essentially only the circuitry already present on the DRAM chip. Thus, the cost of the memory is only insignificantly increased while bandwidth is greatly increased.
An improvement to the fast page mode of operation utilizes an extended data out (EDO) technique. Referring to the timing diagram shown in FIG. 1, in the fast page mode, a data buffer is turned on for data access on the falling edge of a column access strobe (CAS) signal pulse and the data buffer is turned off at the rising edge of the CAS pulse. Using the EDO technique which is shown in the timing diagram of FIG. 2, the data buffers are always turned on. EDO keeps the output drivers on even after CAS goes high. Therefore it is not necessary to wait for valid data to appear before starting the next CAS cycle. Accordingly, the EDO technique allows a shorter CAS clock cycle. By shortening the CAS clock cycle, the speed performance of the memory is improved. The EDO technique furnishes an improvement in memory speed performance over the fast page mode with only an insignificant change in circuitry.
Accordingly, a technique and circuit are needed which improve memory speed performance over the extended data out (EDO) mode of operation and that do not significantly increase circuit size or cost.
The present invention address such a need.